KiCad MCP Pro

Validate that stored DRC exclusions still cover active violations. Re-runs DRC and reports which previously excluded violations are still present (valid) and which have been resolved (stale).

Review whether ICs have nearby decoupling capacitors.

Review diff-pair skew and width symmetry.

Review GND plane presence and a simple void-risk proxy.

Review a high-speed net class for a short-stub proxy.

Check EMC return-path continuity for a signal or all critical high-speed nets.

Warn when routed signals share layers with split non-ground planes.

Estimate via-stitching density from existing ground vias.

Run a lightweight EMC sweep with at least ten heuristic checks.

List known ERC rules and their current severity levels. Severity levels are: ``error``, ``warning``, or ``ignore``.

Reset one or all ERC rule severities back to their default (``error``). Parameters ---------- rule_name : str | None Specific rule to reset, or omit to reset all rules.

Override the severity of an ERC rule. Parameters ---------- rule_name : str Name of the ERC rule (use ``erc_list_rules`` to see available names). severity : str One of ``error``, ``warning``, or ``ignore``.

Interpret a DRC (Design Rule Check) report and explain issues. Accepts raw report text and returns a structured summary with categorized violations.

Interpret an ERC (Electrical Rule Check) report and explain issues. Accepts raw report text and returns a structured summary.

Render a 3D view of the active PCB board to a PNG image. Parameters ---------- output_file : str Output file name (PNG or JPG). Defaults to ``render.png``. side : str View direction: ``top``, ``bottom``, ``front``, ``back``, ``left``, ``right``. zoom : float Camera zoom factor (0.05–20.0). width, height : int | None Output image dimensions in pixels. quality : float | None Rendering quality (0.0–1.0). preset : str | None Render preset name (e.g. ``photo``, ``standard``). use_board_stackup_colors : bool Use the board stackup-defined colors. floor : bool Show the…

Export a bill of materials.

Export BREP format for the active board.

Export drill files.

Export a board layer to DXF when supported.

Export GenCAD format for the active board.

Export GLB format for the active board.

Export IPC-D-356 format for the active board.

Export the active PCB to IPC-2581 format.

Generate the gated manufacturing release package.

Export a KiCad schematic netlist.

Export the active PCB to ODB++ format.

Export the PCB to PDF.

Export pick and place (CPL) data for the active PCB. Parameters ---------- format : str Output format (e.g. ``csv``, ``ascii``). variant : str | None Optional design variant name. When set, exports variant-specific pick-and-place data (component population, value, footprint overrides). Uses the active variant when omitted.

Export PLY format for the active board.

Export PostScript format for the active board.

Export the schematic to DXF when supported.

Export the schematic to PDF.

Export the schematic BOM using KiCad's Python BOM engine.

Export the schematic to SVG when supported.

Export a SPICE netlist.

Export a STEP model for the active board.

Export a STEPZ model for the active board.

Export STL format for the active board.

Export a board layer to SVG when supported.

Export U3D format for the active board.

Export VRML format for the active board.

Export an XAO model for the active board.

Export a KiCad footprint to an interchange format. Supported formats depend on the installed ``kicad-cli`` version. Common values: ``step``, ``svg``, ``dxf``, ``wrl`` (VRML). Parameters ---------- output_path : str Optional output file name (relative to the export directory). Defaults to ``<footprint_name>.<format>``. format : str Target export format. Defaults to ``step``.

Export a footprint or footprint library to SVG format. Parameters ---------- input_path : str Path to the footprint file (.kicad_mod) or library directory (.pretty). output_dir : str Optional output directory. footprint : str Specific footprint name to export within the library. layers : list[str] Optional list of layer names to include. theme : str Optional color theme name. black_and_white : bool Export in black and white only.

Return metadata about the active board's footprint library. Runs ``kicad-cli fp get`` to inspect footprint properties such as 3D model references, layer assignment, and pad count.

Upgrade a KiCad footprint library file to the current file format. Parameters ---------- input_file : str Legacy input file parameter (for backward compatibility). output_file : str Legacy output file parameter (for backward compatibility). input_path : str Path to the footprint library to upgrade. If omitted, input_file is used. force : bool Force resaving regardless of version. dry_run : bool Only report commands and files that would be affected.

Generate an MCP configuration snippet for a supported AI coding agent.

Generate .kicad_dru rules and net-class constraints from the project design intent. Reads power_rails and interfaces from the stored design intent (project_get_design_spec / import_design_spec) and synthesises: - Minimum trace widths from IPC-2221 current-capacity formula (power rails) - Net-class clearance + width + via rules (per-rail) - Differential-pair skew / length / impedance rules (per interface) - HV creepage/clearance rules for rails above 50 V Run drc_check_rule_conflicts() afterwards to surface any conflicts.

Generate a manufacturing readiness report for a KiCad project. Evaluates DRC/ERC status, BOM, and Gerber availability.

Export board statistics and return a readable preview.

Return only courtyard DRC issues for focused follow-up after run_drc.

Return silkscreen overlap issues from DRC.

Return only unconnected DRC issues for focused follow-up after run_drc.

Run a KiCad jobset to produce multiple export artifacts at once. A jobset is a JSON definition file that bundles several export steps (Gerber, drill, PDF, IPC-2581, ODB++, STEP, pick-and-place, BOM, …) into a single ``kicad-cli jobset export`` invocation. The jobset definition is loaded from the project directory or from a template selected via ``jobset_list_templates``. Parameters ---------- output_name : str Optional basename for the output archive (without extension). Defaults to the board basename.

List available KiCad jobset templates. Runs ``kicad-cli jobset list`` and returns the JSON output parsed as a readable summary. Jobset templates define pre-configured batch export workflows (Gerber + drill + PDF + IPC-2581, etc.).

Run a KiCad jobset file against a project. Parameters ---------- project_file : str Path to the KiCad project file (.kicad_pro). If omitted, the active project is used. jobset_file : str Path to the jobset file (.kicad_jobset). This parameter is required. output : str Jobset file output directory or file path. stop_on_error : bool Stop processing jobs sequentially on the first failure of a job.

Validate a KiCad jobset file's basic JSON structure. Parameters ---------- jobset_file : str Path to the jobset file (.kicad_jobset) to validate.

Report how much of KiCad's programmatic surface this server can drive. Answers "can I do X with this server?". Pass ``query`` to search capabilities by keyword or tool name, ``domain`` to list one domain's capabilities, or neither for overall and per-domain coverage plus the biggest open gaps. Coverage % = covered / (total - gui-only-no-api); GUI-only-no-api items are KiCad API limits, not gaps in this server.

Create a new minimal KiCad project structure and activate it.

Show the currently configured KiCad project paths.

Return versioned server information and capability diagnostics for clients.

Get tool names in a category, optionally filtered by maturity.

Get KiCad version information and current connection status.

Show a concise startup guide and all tool categories.

List recently opened KiCad projects from KiCad's config files.

List all available tool categories and capabilities.

Scan a directory and report any KiCad project files it contains.

Set the active KiCad project directory and file paths.

Assign a footprint property to a schematic symbol.

Assign an LCSC part code to a schematic symbol property.

Assign a live part (LCSC/MPN) to a schematic symbol and optionally its footprint. This is the recommended tool for closing the part-selection loop after lib_recommend_part() or lib_search_components() returns a suitable part. Args: sym_ref: Schematic reference designator (e.g. "U1", "C4"). lcsc_code_or_mpn: LCSC part code or manufacturer part number. auto_assign_footprint: If True, attempts to assign the footprint from the live part data to the symbol. Requires the schematic backend. source: Parts source for detail lookup. Returns: Confirmation of LCSC/MPN assign…

Bulk-assign a 3D model to multiple footprints matching a pattern. Parameters ---------- library : str Library name. footprint_pattern : str Regex pattern to match footprint names (e.g. ``SOIC.*``, ``QFP.*``). model_path : str 3D model file path to assign to all matched footprints.

Certify a footprint against package, documentation, and standard checks (#201). Reads the .kicad_mod at ``footprint_path`` (relative to the project) and runs package-agnostic certification: pad count vs the package name (SOIC/QFP/QFN/ SOT/DIP…), documentation-layer completeness (courtyard/fab/silkscreen), and the recorded IPC-7351 density. Returns one aggregate PASS/WARN/FAIL with per-check findings; a missing courtyard or too-few pads is a blocking FAIL. Headless — no KiCad IPC. For two-terminal chip *geometry* use lib_validate_footprint_ipc7351.

Check a part choice for reliability derating and approved-vendor (AVL) compliance. Verifies the operating value stays within the derating limit for the component ``kind``/``parameter`` (e.g. capacitor/voltage <= 80% of rated), and — when ``approved_vendors`` is given — that ``manufacturer`` is on the approved-vendor list. Returns one PASS/WARN/FAIL verdict. Derating factors are conservative general-practice values, not a specific MIL/IPC mandate.

Return a structured sourcing policy verdict for one live part.

Check live stock availability by schematic reference or part number. Provide ``refs`` to look up stock for schematic references (resolving each reference to its part number via the active schematic), or ``mpns`` to look up stock directly by manufacturer part number / LCSC code without needing a schematic. This lets you vet a BOM before the schematic exists. Supply at least one of ``refs`` or ``mpns``.

Create a simple custom symbol in the active project directory.

Find nearby alternative parts for the supplied LCSC code.

Generate an IPC-7351B compliant KiCad footprint (.kicad_mod) and save it. Supported packages: 0201, 0402, 0603, 0805, 1206, 1210, 2512 (chip passives), SOT-23, SOT-223, SOT-89, SOT-363/SOT-26, SC-70/SOT-323, SOD-123, SOD-323, SMA/SMB/SMC (DO-214), DPAK/TO-252, D2PAK/TO-263, SOIC, SOP, SSOP, TSSOP (dual SMD), QFP, LQFP, TQFP (quad flat), QFN, DFN (no-lead), BGA (ball grid array), PinHeader (through-hole). Args: package: Package family name (case-insensitive). density: IPC-7351B density level: A (generous), B (nominal), C (compact). pin_count: Number of leads / balls (required for …

Generate a KiCad symbol (.kicad_sym) from a pin table and save it. Each pin dict must contain: ``number`` (str | int), ``name`` (str). Optional per-pin keys: ``pin_type`` (input/output/bidirectional/passive/power_in/power_out/…), ``side`` (left/right/top/bottom), ``unit`` (int ≥ 1). Args: name: Symbol name, used as both the library entry and the default value. pins: List of pin specification dicts. reference_prefix: Ref-des prefix (U, J, Q, R, …). description: Short human description. datasheet: Datasheet URL or path. footprint_hint: Default footprint (e.g…

Generate a live BOM summary with unit and extended pricing.

Return live component detail for a specific LCSC code or MPN. Displays sourcing metadata (lifecycle, RoHS compliance) and a datasheet URL when the provider reports them.

Return a datasheet URL from the symbol library when available.

Return the configured 3D model path for a footprint.

Return details for a single footprint.

Return details for a single symbol.

List footprints in a specific library.

List configured symbol and footprint libraries.

Rebuild the in-memory symbol search index.

Recommend a purchasable part given electrical requirements. Args: category: Component category keyword to search (e.g. "LDO regulator", "N-channel MOSFET", "ferrite bead", "ESD protection"). requirements: Dict of electrical parameter hints used for post-search filtering. Common keys: ``voltage_v``, ``current_a``, ``vgs_v``, ``rds_on_mohm``, ``psrr_db``, ``capacitance_uf``, ``resistance_ohm``. Values can be numbers (min) or ``{"min": x, "max": y}`` dicts. package: Optional SMD package filter (e.g. "SOT-23", "SOIC-8"). only_basic: Prefer JLCPCB ba…

Remove 3D model reference(s) from a footprint. Parameters ---------- library : str Library name. footprint : str Footprint name. model_path : str | None If provided, only remove the model with this exact path. If omitted, all 3D model references are removed.

Search for available 3D model files in the footprint library directory. Parameters ---------- query : str Search term (case-insensitive, matched against path).

Search live component sources for purchasable parts. ``source``: ``jlcsearch`` (JLCPCB public catalog, no credentials; default), ``nexar`` (requires NEXAR_CLIENT_ID/NEXAR_CLIENT_SECRET), ``digikey`` (requires DIGIKEY_CLIENT_ID/DIGIKEY_CLIENT_SECRET), or ``mouser`` (requires MOUSER_API_KEY). The authenticated sources are inactive until their credentials are configured (loaded from ``.env`` at server startup). Set ``rohs_compliant`` to ``true`` to filter to RoHS-compliant parts only. ``lifecycle`` filters to a specific lifecycle status (e.g. ``Active``, ``NRND``, ``EOL``) when the provider rep…

Search footprint libraries by footprint name. Parameters ---------- query : str Search term (case-insensitive substring match). library_filter : str Optional library name to narrow the search. page : int Page number (1-based). Default 1. page_size : int Results per page. Default 50, max 500.

Search symbol libraries by name, description, or keywords. The query is split into whitespace-separated terms. A symbol matches when EVERY term is found (case-insensitive) in any of its name, description, or keywords (AND across terms, OR across fields). A single-term query behaves as a plain case-insensitive substring match. Parameters ---------- query : str Search terms. Multiple whitespace-separated terms are matched with AND semantics; a single term is a case-insensitive substring match. library_filter : str Optional library name to narrow the search. page : int Page numb…

Set or replace the 3D model path on a footprint. Parameters ---------- library : str Library name (e.g. ``Package_SO``). footprint : str Footprint name (e.g. ``SOIC-8_3.9x4.9mm_P1.27mm``). model_path : str Absolute or relative 3D model file path (Step, VRML, etc.). offset_xyz : str | None Optional offset as ``"x y z"`` in mm (e.g. ``"0 5 0"``). scale_xyz : str | None Optional scale as ``"x y z"`` (e.g. ``"1 1 1"``). rotate_xyz : str | None Optional rotation as ``"x y z"`` in degrees.

Validate a two-terminal chip footprint against its IPC-7351B nominal (hard gate). Reads the .kicad_mod at ``footprint_path`` (relative to the project), parses its SMD pads, and compares pad width/height/pitch to the IPC-7351B nominal for the given chip ``size_code`` and ``density``. Gross deviation is a blocking FAIL, minor deviation WARNs, a match PASSes. Scope: chip passives (0201–2512) against the IPC-7351B *standard* nominal — not a datasheet-specific land-pattern check.

Verify a placed component's symbol, footprint, and pins actually match. For the given schematic reference designator this checks, entirely from local project files (no network access): - symbol pin count vs footprint connectable pad count - pin numbers vs pad numbers - footprint courtyard / fabrication / silkscreen completeness - 3D model presence (advisory) - datasheet evidence (advisory; never auto-filled) Returns a JSON object with a ``status`` of PASS / WARN / FAIL and a list of per-check ``findings``. FAIL marks a structural contract violation, WARN marks a quality/completeness smell, …

Evaluate manufacturing readiness against the active or requested DFM profile.

Report whether the detected KiCad CLI advertises a given board-import format.

Apply JLCPCB CPL rotation corrections to a KiCad-exported pick-and-place CSV. KiCad exports component orientations relative to its own coordinate system, which differs from what JLCPCB's SMT assembly service expects. This tool reads a CPL CSV (produced by export_pos), applies per-footprint rotation offsets from the bundled ``jlcpcb_rotations.json`` table, and writes a corrected CSV ready for direct upload to JLCPCB. Columns expected (KiCad default CPL export): Ref, Val, Package, PosX, PosY, Rot, Side Args: cpl_csv_path: Path to the CPL CSV file (relative to project dir). output…

Generate a machine-readable manufacturing release evidence bundle. Runs compliance gates, checks required artifacts, and produces a signed evidence JSON with a ``release_approved`` / ``release_blocked`` verdict. Gates evaluated: - **Artifact coverage**: Gerber, drill, BOM, and pick-and-place files must exist in the output directory. - **DRC gate**: PCB design rule violations must be zero. - **ERC gate**: Schematic electrical rule violations must be zero. - **HV safety gate**: If ``voltage_v`` > 60 V or ``product_domain`` is ``hazardous_mains``, a ``*.kicad_dru`` file with HV creepage rul…

Generate a SHA256-signed release manifest for the manufacturing package. Collects all files in the output directory, computes SHA256 hashes, and records tool versions, intent hash, and gate status into a ``manifest.json`` and ``MANIFEST.txt``. Args: output_path: Subdirectory inside the project (defaults to ``output/``). Returns: Confirmation with manifest path and file count.

Generate a bring-up test plan from the project design intent. Produces a structured markdown checklist covering: - Power-on sequence and current limit checks for each power rail. - Protocol loopback / link-up checks for each interface. - Critical-net continuity probes. - Visual inspection items. Args: output_path: Optional relative path for saving the plan (e.g. ``"test_plan.md"``). If omitted, returns the plan as text only. confirm_overwrite: If True, allow overwriting an existing output file. Returns: Bring-up test plan in markdown format.

Import an Allegro board into a KiCad project directory.

Import a gEDA PCB into a KiCad project directory.

Import a PADS PCB into a KiCad project directory.

Import a Specctra DSN/SES file into a KiCad project directory.

Panelize the active PCB using KiKit. Creates a panel of multiple boards for efficient PCB fabrication. Requires ``kikit`` to be installed (``pip install kikit``). Args: layout: Panel layout type: ``"grid"`` (rectangular array), ``"mousebites"`` (tab+mousebite breakaway), or ``"vcut"`` (V-cut scoring). rows: Number of board rows in the panel. cols: Number of board columns in the panel. spacing_mm: Gap between boards in mm. frame_width_mm: Panel frame/rail width in mm. output_path: Optional output file path (relative to output_dir). Defaults to ``panel/<…

Begin a transaction group for atomic board modifications. All subsequent mutations (add, remove, update operations) will be grouped into a single undo step in KiCad. Call pcb_push_commit to apply or pcb_drop_commit to discard. Returns: Confirmation message with commit status.

Drop (discard) the current transaction group without applying changes. All mutations since pcb_begin_commit will be discarded. Returns: Confirmation message with drop status.

Export the PCB to a 3D PDF. Parameters ---------- output_path : str Output file name (relative to the export output directory).

Export board statistics (net count, component count, layer count, etc.) via the KiCad CLI ``pcb export stats`` command. Parameters ---------- output_name : str | None Optional output file name (saved under the project output directory). Defaults to ``board_stats.json``.

Return the current board as a bounded S-expression string.

Summarize the current board.

List every layer referenced by a footprint block, including inner layers.

List board footprints.

List board groups (KiCad 10.0.0+). Groups are logical collections of board items that can be moved and manipulated together. Returns: JSON string with group information or message if not supported.

List enabled board layers.

Return sanitized native-live PCB transaction state as deterministic JSON.

Return statistical data about all nets in the active PCB. Includes per-net counts of tracks, vias, pads, and total track length (mm). Uses an active KiCad IPC connection when available; falls back to file-level net enumeration.

List all board nets.

Get the current board origin (drill origin) in millimeters. Returns: JSON string with origin coordinates or message if not supported.

List board pads.

List currently selected items in the PCB editor.

List graphical board shapes.

Show the current stackup.

List board tracks.

List board vias.

List all board copper zones.

Import a non-KiCad PCB file to KiCad format. Parameters ---------- input_file : str Path to the non-KiCad board file. output_file : str Optional path for the imported KiCad PCB file. format : str Input format: auto, pads, altium, eagle, cadstar, fabmaster, pcad, solidworks. report_format : str Import report format: none, json, text. report_file : str Optional file path for the import report.

Inspect every detail about a specific net in the PCB. Parameters ---------- net_name : str The exact net name to inspect (e.g. ``GND``, ``+3V3``, ``USB_DP``).

Evaluate whether footprint placement is overlap-free and inside the board frame.

Return a structured placement-quality report for capable MCP clients.

Push (commit) the current transaction group to the board. All mutations since pcb_begin_commit will be applied as a single undo step. Returns: Confirmation message with commit status.

Evaluate whether the PCB is physically clean enough to proceed.

Revert the board to the last saved state, discarding all unsaved changes. WARNING: This is a destructive operation. All unsaved modifications will be lost. Returns: Confirmation message with revert status.

Check whether routed tracks still contain non-professional 90-degree corners.

Score PCB placement quality and explain both hard failures and softer warnings.

Set the board origin (drill origin) in millimeters. The origin is used as the reference point for drill files and some export formats. Args: x_mm: X coordinate in millimeters. y_mm: Y coordinate in millimeters. Returns: Confirmation message with new origin coordinates.

Set the active board stackup using a file-backed profile.

Set board title block information (KiCad 10.0.1+). Title block fields appear on printed outputs and drawings. Args: title: Board title. date: Board date. revision: Board revision. company: Company name. comment1: Custom comment field 1. comment2: Custom comment field 2. comment3: Custom comment field 3. comment4: Custom comment field 4. Returns: Confirmation message with updated fields.

Validate board layer table and stackup copper layer consistency.

Evaluate whether named schematic pad nets transferred cleanly onto PCB pads.

Upgrade a PCB file to the current KiCad file format. Parameters ---------- input_file : str Path to the PCB file (``.kicad_pcb`` or legacy ``.brd``) to upgrade. If omitted, the active project's PCB is used. output_file : str Optional output path. Defaults to the input path (in-place). force : bool Force resaving regardless of version. dry_run : bool Only report commands and files that would be affected.

Headless PCB readability QA: off-board parts, silk and body overlap. A fast, file-backed first pass that runs without a live KiCad: it flags footprints whose body leaves the board outline, reference designators that collide on the silkscreen, and overlapping footprint bodies — directly from the ``.kicad_pcb`` geometry. It complements (does not replace) the authoritative DRC run, which remains the sign-off check for courtyard and silk clipping. Returns JSON with an overall PASS/INFO/WARN status and per-finding refs/positions.

Estimate DC voltage drop, trace resistance, and IPC-2221 current-density fusing. ``max_temp_rise_c`` is the temperature-rise budget; the verdict is PASS within it, WARN up to 2x, FAIL beyond. Set ``internal_layer=True`` for a buried trace (lower ampacity).

Check whether the routed copper for a net looks sufficient for the load current.

Generate a rectangular copper plane on the requested copper layer.

Recommend local and bulk decoupling from a simple PDN heuristic.

Scope re-validation after an edit: semantic-diff the design intent and report which gates must re-run. Compares a baseline design spec — the declared/saved intent, or an explicit baseline passed as ``baseline_spec_json`` — against the intent inferred from the current board, then maps each change to the gates it can invalidate. Re-run only the impacted gates and keep the rest as already-proven. Use after editing an existing project so a small change does not force a full re-validation.

Run the project quality gate and automatically apply server-side fixes. Each iteration: 1. Evaluates all project quality gates. 2. For **auto-applicable** gates (annotation, zone refill) — calls the underlying fix implementation directly on the server, then re-evaluates. 3. For gates requiring **agent action** — returns the tool name and description so the agent can call it, then the agent must call this tool again to continue. The loop runs up to ``max_iterations`` times applying auto-fixes. It stops early when all gates pass or when no further auto-fix is possible without agent i…

Generate a comprehensive design-status report. Combines intent summary, v2 spec richness, project gate evaluation, and a prioritised list of next steps into a single structured report. This is the recommended first call after opening a project to understand its current state.

Return the professional PCB design workflow as a typed phase state machine. Lays out the canonical Planner -> Builder -> Verifier -> Fixer -> Release sequence, with the high-level tool and the quality gates each phase must pass. Pass the phases already finished in ``completed_phases``; the tool marks them COMPLETE, reports the first remaining phase as READY (the current step) with its next action and gates, and flags when a human gate is required. Read-only and headless — use it to drive an autonomous design run step by step.

Embed an external file into the KiCad project as project metadata. The file content is stored inline inside the ``.kicad_pro`` JSON. Large files (over 1 MB) are rejected to keep project files manageable. Parameters ---------- source_path : str Absolute or relative path to the file to embed. target_name : str | None Name to store the file as (defaults to the source file name). description : str Optional human description of the embedded file.

Extract an embedded file from the project and write it to disk. Parameters ---------- name : str Name of the embedded file to extract (see ``project_list_embedded_files``). output_path : str | None Destination file path. If omitted, extracts to the project directory using the embedded file name.

Run ERC/DRC/project gates in a bounded fix-and-rerun validation loop.

Return persisted quality-gate trend history for one gate.

Generate a professional workflow prompt tailored to the resolved project spec.

Show the persisted project design intent used by placement and release gates.

Return the resolved project design spec with explicit and inferred fields.

Return the next high-priority action derived from the current project gate.

Import structured product/spec text into ProjectDesignIntent conservatively. Accepts JSON or YAML frontmatter/fenced blocks. The importer only persists explicit supported ProjectDesignIntent fields; it reports missing mandatory decisions, placeholders, and extra fields such as MPN/LCSC/populate lists without inventing values. Use ``dry_run=True`` first, then re-run with ``dry_run=False`` after reviewing the parsed result.

Infer a design spec from the active PCB without writing it to disk.

List all embedded (project-embedded) files in the active project. Returns a JSON array of embedded file entries with their metadata (name, source path, description).

Run the professional release gate bundle before manufacturing handoff.

Run the full project quality gate across schematic, PCB, DFM, and parity checks.

Return the full project gate in structured form for capable MCP clients.

Assemble a release-readiness evidence bundle for human manufacturing review. Aggregates project gate results, DRC/ERC summaries, BOM completeness, waiver state, release artifacts, and manifest presence into one structured, text-renderable payload. Missing required evidence fails closed. When ``output_path`` is provided, the bundle is also written as JSON, Markdown, HTML, or a print-friendly HTML report (``pdf-ready``).

Remove an embedded file entry from the project metadata. Parameters ---------- name : str Name of the embedded file to remove.

Re-run only the gates an edit could have invalidated; prove the rest preserved. Computes the semantic intent diff (like ``project_assess_edit_impact``), then actually re-runs only the impacted project gates -- skipping unaffected ones -- so a small edit does not force a full re-validation. Impacted analysis categories that the sign-off gate does not cover (signal integrity, power, thermal, EMC) are listed with the tool to re-run for each.

Persist high-level project design intent and structural group constraints.

Produce the single manufacturing sign-off report. Binds each declared design-intent requirement to the gate check(s) that would catch a violation, attaches the gate evidence and full provenance (engine versions, rule profile, intent and source hashes), and returns one PASS/FAIL verdict. A board with no declared intent is UNVERIFIED, not a silent PASS. ``export_manufacturing_package`` is hard-gated on the same underlying project gate, so a PASS here means the package will export.

Validate the resolved design spec against the active project PCB.

Compare the two fixed manufacturing snapshot manifests after byte revalidation.

Generate one of two fixed fresh manufacturing snapshots for benchmark evidence.

Apply a routed Specctra SES to the active board headlessly -- no GUI step. KiCad has no headless SES import, so this parses the routed session and writes its segments and vias directly into the .kicad_pcb via the round-trip-safe S-expression layer; the rest of the board file is untouched. Re-applying the same session is deterministic and idempotent (it replaces, not duplicates, the routing). This closes the manual File > Import > Specctra Session step. Run run_drc() afterwards to verify.

Assign a named tuning profile to a net or wildcard net group.

Run FreeRouting after placement, then surface the KiCad import step. DSN export is attempted headlessly; FreeRouting runs via Docker or a local JAR. Applying the routed SES session back to the board has no headless path in KiCad, so this returns a human-gated result (``human_gate_required=True``) describing the File > Import > Specctra Session step — it does not claim the board is routed when the session has only been staged. If headless DSN export is unavailable, the manual export step is surfaced instead of failing opaquely. When the experimental MCP Tasks extension is enabled (``KICAD_MCP…

Create or update a KiCad 10-style time-domain tuning profile.

Write differential-pair routing constraints for a pair of nets.

Export a Specctra DSN for FreeRouting; may require a one-time KiCad GUI step. Uses headless ``kicad-cli pcb export specctra`` when the CLI supports it. If KiCad cannot export the DSN headlessly, returns a human-gated result describing the File > Export > Specctra DSN step instead of failing opaquely.

Create a simple orthogonal route between two pads.

Stage a routed Specctra SES and surface the required KiCad GUI import step. KiCad has no headless SES import, so this stages the session and returns a human-gated result: the routing is applied by running File > Import > Specctra Session in the PCB Editor. It never reports the board as routed when it is not (``changed=False``, ``human_gate_required=True``).

List configured time-domain tuning profiles.

Write net-class routing constraints into the active .kicad_dru file.

Route a single straight track segment.

Write a length-tuning rule and report the current delta for a net.

Create a time-domain tuning rule for one concrete net; wildcards are rejected.

Return full DRC report with PCB violations, unconnected items, and courtyard issues.

Run schematic electrical rule checks.

Add a schematic bus, snapping endpoints to the 1.27 mm / 50 mil grid by default.

Add a bus wire entry marker. Snaps its anchor to the 1.27 mm / 50 mil grid by default.

Add a schematic component through the hybrid IPC reload path.

Add a global label, preserving the requested shape and rotation. By default the text is justified away from the directional icon based on ``rotation`` (0=left, 90=bottom, 180=right, 270=top) so it doesn't render on top of the icon. Pass ``justify`` to override, or "none" to force KiCad's centered default.

Add a hierarchical label, preserving the requested shape and rotation. By default the text is justified away from the directional icon based on ``rotation`` (0=left, 90=bottom, 180=right, 270=top) so it doesn't render on top of the icon. Pass ``justify`` to override, or "none" to force KiCad's centered default.

Add a jumper symbol to the schematic.

Add a schematic label, snapping its anchor to the 1.27 mm / 50 mil grid by default. ``justify`` overrides KiCad's centered default (e.g. "left", "right", "top", "bottom", "left top"); local labels have no directional icon so centered text is usually correct and this is rarely needed.

Place many labels in one call, snapping each to the 1.27 mm / 50 mil grid. Each ``labels`` entry is a dict: ``name``, ``x_mm``, ``y_mm`` and optional ``rotation``, ``kind`` ("local"|"global"|"hierarchical"; default "local"), ``shape`` (for hierarchical/global labels), ``justify`` and ``snap_to_grid``. An invalid ``kind`` names the offending entry index.

Insert missing schematic junctions at T-intersection wire endpoints.

Add a no-connect marker, snapping it to the 1.27 mm / 50 mil grid by default.

Connect placed-symbol pins to nets with a short outward wire stub plus a terminal placed clear of the symbol body (avoids label-on-pin overlap). Each connection is ``{"reference": "U3", "pin": "VIN" | "5", "net": "5V_SYS"}``; the pin may be a number or a name. The stub direction is derived from the symbol edge the pin sits on, so the terminal lands outside the symbol and reads outward. Power nets get conventional power symbols; other nets get labels. Pins that share a ``net`` are joined by their common terminal name. This is the clean alternative to placing bare labels directly on pins. ``la…

Add a power symbol, snapping its anchor to the 1.27 mm / 50 mil grid by default.

Add one hierarchical sheet pin to a sheet symbol at an explicit position. ``position_along_edge`` runs clockwise from the right edge: ``right`` measures from the top, ``bottom`` and ``top`` from the left, and ``left`` from the bottom. Use ``sch_import_sheet_pins`` to derive every pin from the child sheet instead of placing them one by one. Limitations, all deliberate: - The position is used exactly as given. It is **not** snapped to the schematic grid, so a pin placed off-grid will have no wire snap to it. ``sch_import_sheet_pins`` does snap. - A position past the end of an edge is acce…

Add a schematic symbol at an absolute coordinate. Coordinates snap to the 1.27 mm / 50 mil schematic grid by default; set snap_to_grid=False only when an exact off-grid coordinate is intentional.

Add a schematic wire, snapping endpoints to the 1.27 mm / 50 mil grid by default.

Snap off-grid symbols, labels, wires, and junctions onto the drawing grid. Off-grid anchors are the top cause of ragged sheets and wires that visibly miss their pins. Symbols translate as a whole so pins stay aligned. Runs as a dry run by default (reports the moves and whether connectivity is preserved); pass apply=true to commit. Apply is refused if it would change any net.

Preview how netlist-aware schematic compilation will resolve endpoints and wires. Mirrors ``sch_build_circuit``: by default nets resolve to collision-safe terminal stubs; pass ``unsafe_routed_wires=True`` to preview routed Manhattan wire segments instead.

Renumber schematic references sequentially.

Checkpoint the schematic, then apply the plan's net labels. Copies every schematic file into a per-plan checkpoint before mutating, so ``sch_rollback_plan`` can fully restore the prior state. The label insertion runs through the project's atomic, validating writer.

Place schematic symbols into semantically meaningful zones on the sheet. Unlike the basic ``sch_auto_place_symbols`` which uses a plain grid, this tool categorises each symbol by its **function** (MCU, connector, power IC, sensor, passive, protection …) and places it in the corresponding region of the schematic sheet. The result is a readable, professionally structured schematic with logical signal flow (connectors on the left, processing in the centre, power/decoupling at the bottom). Zone layout (column × row, each cell = 25.4 × 17.78 mm):: Col → 0-2 3-5 6-8 …

Place selected references with a deterministic cluster, linear, star, or grid layout. Unlike the legacy behaviour, this version reads all already-placed symbols first and avoids placing new symbols on top of them. Fixed/already-placed symbols that are not in ``symbol_list`` are treated as immovable obstacles.

Automatically grow the sheet to fit all currently placed symbols. Reads the bounding box of all placed symbols and selects the smallest standard paper size (A4 → A3 → A2 → A1) that contains them with the configured margin. If the current sheet already fits, reports that no change is needed. Returns: The chosen paper size and new dimensions, or a message if the current size is already sufficient.

Reposition symbol Reference/Value text onto the clearest body side. Mirrors KiCad's ``autoplace_fields``: for each symbol the visible Reference and Value fields are moved to the body side with the most clearance, away from pins and neighbouring symbols, so the rendered sheet stops stacking text on top of other text. Footprint/Datasheet and hidden fields are left untouched. Pass ``references`` to limit the operation to specific designators, or ``dry_run`` to preview the count without writing. Run this after ``sch_auto_place_symbols`` (or any bulk placement) and use ``sch_visual_qa`` to confir…

Build (overwrite) the active schematic from structured symbol, wire, and label inputs. IMPORTANT: This tool **replaces** the entire schematic content. Any symbols already placed in the schematic will be lost. To add symbols to an existing schematic without erasing it use ``sch_add_symbol`` / ``sch_add_wire`` / ``sch_add_label`` instead. Coordinates are snapped to the 1.27 mm / 50 mil grid by default. When no coordinates are provided for a symbol, set ``auto_layout=True`` so the placement engine assigns non-overlapping positions automatically. When ``nets`` are provided, the builder is co…

Score the active schematic's cosmetic quality on a 0-100 scale. Extends readability QA with the traits that separate a professional sheet from a merely-working one: on-grid placement, orthogonal wiring, consistent typography, upright power/ground symbols, and balanced sheet composition. Returns a deterministic per-sheet and overall score with a per-category penalty breakdown and the worst category to fix first — the loop signal for the visual-excellence workflow. No rendering or live KiCad required.

Create a child schematic sheet and add it to the active top-level schematic. Optional ``sheet_pins`` is a list of ``[name, type]`` two-element arrays, laid out by the same rules as ``sch_import_sheet_pins``.

Delete label(s) (local/global/hierarchical) matching ``name`` at the given coordinate. Use sch_get_labels() to find exact names/positions.

Delete the no-connect marker(s) at the given coordinate. Use sch_get_symbols()/sch_get_connectivity_graph() to find pin positions.

Remove the hierarchical sheet named ``name`` (its ``Sheetname``) from the parent. Deletes the whole ``(sheet ...)`` block including its instance/path bookkeeping -- the inverse of ``sch_create_sheet``. The child file is left in place. Reports if the name is not found.

Remove a placed symbol and any directly attached wire segments.

Remove a specific wire segment using its UUID or unique UUID prefix.

Find N collision-free placement coordinates for new symbols. Reads the current schematic, builds an occupancy grid from all existing symbols, and returns ``count`` coordinate pairs that do not overlap with any placed symbol. Call this before sch_add_symbol to get safe (x, y) values. Args: count: Number of free coordinate slots to return (default 1, max 64). cell_width_mm: Grid cell width in mm (default 25.4 — one 10-mil grid unit). cell_height_mm: Grid cell height in mm (default 17.78). keepout_regions: Optional rectangular keepouts as ``[(x_min, y_min, x_max, y_max)…

Iteratively fix schematic readability defects until clean or stable. Runs the headless ``sch_visual_qa`` checks, then applies the matching fixer and re-checks, looping until the sheet passes, no further progress is made, or ``max_passes`` is reached: - **off-sheet** symbols/labels -> grow the sheet one paper size (A4 -> A3 ...) - **text overlap** -> auto-place Reference/Value fields onto clear body sides - **symbol-body overlap** -> re-space the symbols on a body-sized grid, but ONLY when the sheet has no wires, labels or power symbols (moving a connected symbol would break its nets); ot…

Return the estimated bounding box of every symbol in the active schematic. Use this before calling sch_add_symbol or sch_build_circuit to understand which areas of the schematic sheet are already occupied. The bounding boxes are heuristic estimates (KiCad does not expose exact extents via the file API) but are conservative enough to avoid overlap in practice. Returns: A table of all symbols with their centre position and estimated bounding-box corners (x_min, y_min, x_max, y_max) in mm, plus an occupied-area summary.

Return the semantic circuit IR for the active schematic. The IR decouples 'what the circuit is' (components, nets, pin roles, power domains, interfaces) from 'how KiCad stores it' (geometry, UUIDs, file format). Wiring is expressed in terms of pin names and roles, not coordinates. The output is a structured text summary of the IR.

Return full details for a subcircuit template. Args: template_name: Template name as returned by sch_list_templates() (e.g. ``"buck_converter_generic"``). Returns: Structured template description including parameters, symbols, nets, and placement hints.

Mirror each child sheet's hierarchical labels as pins on its sheet symbol. This is KiCad's "Import Sheet Pins" without the GUI: without these pins the sheets are electrically separate, ERC reports ``hier_label_mismatch`` for every label, and a net that crosses sheets appears twice in the netlist. Inputs are laid out on the left edge and every other pin type on the right, alphabetically; the sheet symbol grows taller if it must. Every pin of a touched sheet is re-laid-out, including existing ones, because KiCad measures left-edge pins from the bottom -- so a growing sheet would otherwise move…

Instantiate a subcircuit template — returns a structured action plan. This tool returns a structured plan describing the symbols, connections, and part-search steps needed to add the subcircuit to the schematic. It does NOT directly edit the schematic (use the plan as a guide for calling sch_add_symbol, sch_add_wire, lib_recommend_part, etc.). Args: template_name: Template name (from sch_list_templates()). prefix: Reference prefix applied to all template refs (e.g. ``"PWR_"`` produces ``PWR_U1``, ``PWR_L1``, etc.). params: Dict of parameter overrides (e.g. ``{"vout_v": 5.…

List candidate pins and units that can participate in a swap workflow.

List all available reference subcircuit templates. Templates are pre-wired subcircuit blueprints for common building blocks (buck converter, LDO, USB Type-C, MCU decoupling, Ethernet with magnetics). Call sch_get_template_info() for full parameter and placement details, then sch_instantiate_template() to add the subcircuit to the schematic.

Poll a safe live schematic preview state and refresh rendered output on changes. This is an opt-in polling watcher for agents and companion-plugin flows. It records the current schematic file signature, debounces rapid writes, then refreshes a PNG preview when the watched files are stable. KiCad GUI reload is deliberately opt-in via ``reload=True`` because the tool cannot reliably prove that the user has no unsaved GUI edits.

Set the text justification of an existing label (local/global/ hierarchical) matching ``name`` at (x_mm, y_mm). Use sch_get_labels() to find exact names/positions. Global and hierarchical labels carry a directional icon at their anchor; KiCad centers unjustified text on that anchor, which overlaps the icon. Pass "left", "right", "top", "bottom", or a combination like "left top" to move the text clear of the icon, or "none" to restore KiCad's centered default.

Modify a schematic symbol property by reference.

Move the label matching ``name`` at (x_mm, y_mm) to a new coordinate, optionally re-rotating it. snap_to_grid defaults to False so the anchor can land exactly on a pin/wire endpoint.

Move the hierarchical sheet named ``name`` (its ``Sheetname``) to a new anchor. Only the sheet's ``(at ...)`` anchor and its pins move; each pin keeps its offset and rotation. Size, styling, UUIDs and the child file are untouched.

Move an existing symbol instance to a new absolute coordinate.

Upright sideways power/ground symbols, rotating about the pin to keep the net. Rotates 90/270-degree power symbols to upright and translates them so the pin stays on its original coordinate. Dry run by default; apply=true commits, and is refused if the net would change.

Normalise outlier font sizes onto the sheet's dominant size. Connectivity-neutral typography cleanup over placed-symbol and label text only (never the library cache). Dry run by default; apply=true commits.

Create a stored schematic change plan from a JSON spec (no write). The spec describes a small subcircuit as ``components`` (reference + lib_id, optional value/footprint) and ``labels`` (text + x/y) plus optional ``nets`` and ``title``. Returns the content-addressed ``plan_id`` to use with the preview/apply/verify/rollback tools.

Return the object changes a plan would make, without writing anything.

Ask KiCad to reload the active schematic.

Render a schematic sheet to PNG for visual self-checks. Uses headless ``kicad-cli sch export svg`` followed by SVG-to-PNG conversion. Empty sheets return ``status=empty_sheet`` instead of a misleading blank image.

Render the exact visual delta produced by the last schematic mutation. The red pixels are the aligned before/after image difference. Metadata lists every changed symbol, label/net, wire, bus, junction, or document object.

Flip the justify of overlapping labels so their text stops colliding. Connectivity-safe by construction: the label anchor never moves, only the rendered text direction. Dry run by default; apply=true commits.

Restore the schematic from a plan's checkpoint, undoing the apply.

Route deterministic Manhattan wire segments between two placed symbol pins.

Set KiCad's native Do Not Populate flag on a placed symbol. When ``reason`` is given it is stored in the ``DNP Reason`` property so ``sch_get_population_status`` and variant BOMs can report why the part is unpopulated.

Toggle KiCad 10 hop-over display in the active project settings.

Change the schematic sheet (paper) size. Use this when the current sheet is too small to fit all symbols — for example after ``sch_auto_place_functional`` warns that symbols were placed outside the sheet boundary, or when you receive a screenshot showing components outside the red sheet border. Supported sizes (landscape): A4, A3, A2, A1, A0, A (letter), B, C, D, E, USLetter, USLegal. After resizing you should call ``sch_auto_place_functional`` again so that symbols are re-distributed across the larger sheet. Args: paper: Target paper size keyword (default "A3"). Returns: Confirma…

Set schematic title block fields on the root sheet or a child sheet. Unspecified fields are preserved. Use ``sheet`` for a named child sheet or ``sheet_file`` for a specific ``.kicad_sch`` file; omit both to target the active root schematic.

Move sheet-symbol columns apart to make room for stub-and-label wiring. Sheets are grouped into columns by overlapping x-span, and only whole columns move -- and only to the right, never left and never vertically. Run this **before** ``sch_wire_sheet_pins``, not after: it refuses to move a sheet already wired on a pin, since that would silently disconnect the wire (KiCad joins on exact coordinate equality), and ``sch_wire_sheet_pins`` wires every pin it touches by default. If any sheet that must move has a wired pin, the **whole** spread is refused, not just that sheet's own column, since a p…

Straighten almost-orthogonal wire segments onto the horizontal/vertical axis. Diagonal wires read as rushed; small off-axis deltas are snapped flat. Dry run by default; apply=true commits, and is refused if a straighten would change connectivity.

Record a gate-swap back-annotation intent for a multi-unit component.

Record a pin-swap back-annotation intent for a component.

Update a property on a placed symbol.

Upgrade a schematic file to the current KiCad file format. Parameters ---------- input_file : str Path to the schematic file (``.kicad_sch`` or legacy ``.sch``) to upgrade. If omitted, the active project's schematic is used. output_file : str Optional output path. Defaults to the input path (in-place). force : bool Force resaving regardless of version. dry_run : bool Only report commands and files that would be affected.

Verify an applied plan against the schematic; report ERC availability. Verification fails closed when planned labels or components are absent, planned labels are unattached, or connectivity analysis cannot complete. Full ERC is declared explicitly as available or unavailable rather than silently skipped — run ``run_erc()`` for the full electrical gate.

Compare a sheet's current render against its stored visual baseline. Renders the sheet, diffs it pixel-wise against the baseline, and reports the drift percentage, the changed bounding box, and a highlighted diff image. Status is ``PASS`` when drift is within ``threshold_pct``, else ``DRIFT``. Reports ``no_baseline`` if the sheet was never captured.

Capture the current render of a schematic sheet as its visual baseline. Renders the sheet headlessly and stores the PNG plus metadata (dpi, source hash) under ``.kicad-mcp/visual_baselines/``. Call this once a sheet looks right; ``sch_visual_baseline_compare`` then flags any later visual drift.

Run headless visual/readability QA on the active schematic sheet(s). Detects readability defects ERC cannot — overlapping labels, off-sheet symbols or labels, dense unreadable label fanout, and title-block gaps — directly from the schematic S-expression geometry, with no rendering required. Returns JSON with an overall PASS/WARN/FAIL status and per-sheet findings carrying object refs and positions for follow-up.

Connect sheet pins by giving each one a wire stub and a local label. A sheet pin alone joins nothing -- two sheets become one net only once something in the parent schematic connects their pins, and matching names are not enough (unlike global labels). This writes a short wire stub out of every sheet pin, then a **local** label carrying the pin's name at the far end. Same-named local labels on one sheet are one net; that is what actually joins the sheets, not the pins themselves, and no wire ever has to route between sheet symbols (crossing wires in KiCad merge geometrically into silent short…

Evaluate whether schematic structure and hierarchy look electrically meaningful.

Check the schematic against professional electrical-design rules (advisory). Beyond ERC connectivity: flags supply rails that feed ICs without a decoupling capacitor and I2C buses without pull-up resistors. This is an advisory critic (WARN), not a hard release gate, so it complements ``run_erc()`` rather than replacing it.

Evaluate whether the schematic is clean enough to proceed.

Search KiCad documentation and knowledge base for PCB design topics.

Estimate high-speed channel insertion loss and eye opening for a lossy trace. Sums conductor skin-effect and dielectric (tan-delta) loss to get insertion loss at the Nyquist rate, then a first-order loss-limited eye height, with a PASS/WARN/FAIL verdict against ``max_insertion_loss_db``. When an ngspice CLI is available the insertion loss is measured from an RLGC-ladder AC sweep; otherwise a closed-form estimate is used. The method label states which path produced the numbers.

Map interface specs from the project design intent to KiCad net classes. For each interface with an impedance target, this tool generates the pcb_set_net_class() calls needed to enforce clearance and diff-pair rules. When ``dry_run=True`` (default), only returns the plan without executing it. Args: interfaces: List of InterfaceSpec dicts from project_get_design_spec(). dry_run: If True, return the mapping plan without modifying the project. Set to False to have the tool call pcb_set_net_class() for each class. Returns: Net class plan or confirmation of changes applied.

Estimate decoupling placement quality around an IC power pin.

Estimate PCB trace impedance using quasi-static interconnect formulas.

Solve for a trace width that meets the requested impedance target.

Estimate differential-pair length skew and delay mismatch from board tracks. Returns a PASS/WARN/FAIL verdict. The skew budget comes from ``skew_budget_ps`` if > 0, otherwise from the matching design-intent interface, otherwise a conservative default. PASS within budget, WARN up to 2x budget, FAIL beyond.

Estimate via-stub resonance and risk for selected vias on the active board. ``via_positions`` are ``[x_mm, y_mm]`` two-element arrays.

Generate a practical board stackup recommendation and target trace geometry.

Report configured solver-grade analysis capabilities and unavailable seams.

List all built-in dielectric materials with Er, loss tangent, and frequency range. Use the returned material keys with si_synthesize_stackup_for_interfaces() to select the appropriate laminate for your design.

Synthesise a PCB stackup that meets the impedance requirements of the given interfaces. Analyses each InterfaceSpec dict and recommends: - Layer count - Dielectric material - Copper weight per layer - Outer dielectric thickness for target impedance - Net class settings (impedance, clearance, diff-pair gap) Args: interfaces: List of InterfaceSpec dicts (matching project_set_design_intent interface format). Each must have at least ``kind`` and optionally ``impedance_target_ohm``, ``differential``, ``diff_skew_max_ps``. cost_tier: ``"standard"`` (FR4), ``"midloss"`` (FR4…

Validate that each net group is matched within the supplied tolerance.

Persist a SPICE directive used by future MCP simulation runs.

Register a SPICE model library in the active project file. Parameters ---------- name : str Display / key name for the library entry. uri : str Path or URI to the SPICE model file. Absolute paths, relative paths (resolved from the project directory), and KiCad environment variable references (e.g. ${KICAD_USER_LIB}) are all valid.

Assign SPICE model properties to a component in the active schematic. Sets Sim.Name, Sim.Library, Sim.Type, Sim.Pins, and Sim.Params symbol properties. Empty strings are skipped so you can update a single field without overwriting the others.

Estimate loop crossover and phase margin from an AC sweep.

List SPICE model libraries registered in the active project.

Unregister a SPICE model library from the active project file.

Run a small-signal AC sweep.

Run a DC sweep for an independent source.

Run a DC operating-point analysis.

Run a transient time-domain simulation.

Check that registered SPICE libraries are resolvable from the project directory.

Update the active IDE context pushed by KiCad Studio.

Export a KiCad symbol to an interchange format. Supported formats depend on the installed ``kicad-cli`` version. Common values: ``svg``, ``pdf``. Parameters ---------- output_path : str Optional output file name (relative to the export directory). Defaults to ``<board_name>.<format>``. format : str Target export format. Defaults to ``svg``.

Export a symbol or symbol library to SVG format. Parameters ---------- input_file : str Path to the symbol library file (.kicad_sym). output_dir : str Optional output directory. symbol : str Specific symbol name to export within the library. theme : str Optional color theme name. black_and_white : bool Export in black and white only. include_hidden_pins : bool Include hidden pins in the SVG export. include_hidden_fields : bool Include hidden fields in the SVG export.

Upgrade a KiCad symbol library file to the current file format. Parameters ---------- input_file : str Path to the symbol library file (``.kicad_sym``) to upgrade. If omitted, the active schematic's symbol library is used. output_file : str Optional output path. Defaults to overwriting the input. force : bool Force resaving regardless of version. dry_run : bool Only report commands and files that would be affected.

Estimate thermal via count from package heat and board thermal resistance.

Check whether the board already has copper pour support for the net.

Solve copper-plane heat spreading with a 2-D finite-difference thermal solver. Models a hot source dissipating ``power_w`` into a copper plane that loses heat to ambient through both faces (``film_coefficient_w_per_m2_k`` is the combined top+bottom film coefficient). Returns the peak and average temperature rise from a genuine distributed steady-state solve, with a PASS/WARN/FAIL verdict against ``max_temp_rise_c``. This is a 2-D spreading solve, not a 3-D FEA with airflow.

Write matched-length rules for both nets in a differential pair.

Run DRC and ERC and summarize readiness.

Compare PCB footprint references against the schematic symbol references.

Clone an existing design variant under a new name. Parameters ---------- name : str Source variant name. new_name : str Target name for the cloned variant.

Create a new design variant, optionally cloning an existing variant.

Delete a design variant. Parameters ---------- name : str Variant name to delete. Cannot delete the ``default`` variant.

Diff the effective BOM between two design variants.

Export a variant-specific BOM into the project output directory.

Export a manufacturing package for a specific variant. Combines Gerber, drill, BOM, and pick-and-place exports with the variant's overrides applied. Parameters ---------- variant : str Variant name. output_name : str | None Output filename for the package manifest (defaults to ``<variant>_manufacturing.json``).

Export a variant-specific schematic PDF with overrides applied. Parameters ---------- variant : str Variant name. output_name : str | None Output filename (defaults to ``<variant>_schematic.pdf``).

Get the effective status of a single component in a variant. Parameters ---------- variant : str Variant name. reference : str Component reference designator (e.g. ``R1``, ``C4``).

List available design variants and basic component counts.

Set the active design variant for the current project.

Override component population, value, or footprint in a variant.

Commit the current project state as a named checkpoint.

Show the current project diff versus a checkpoint commit.

Initialize a Git repository for the KiCad project directory.

List checkpoint commits created by the MCP tool.

Restore project files and keep a recovery branch for the stashed pre-restore state.

Create an annotated release tag after the full project quality gate passes.