Easyeda MCP Pro

Zoom the EasyEDA canvas to a coordinate/scale (document/canvas coordinates), returning the resulting viewport rectangle. Useful to frame a location before calling easyeda_canvas_capture, or standalone to navigate the user's view to a point of interest.

List devices cached by easyeda_catalog_verify_device, with their validation status and provenance. Optionally filter by status (resolved/partial/unresolved). This is a local cache only — never redistributed.

Resolve an LCSC part number into a catalog device entry (keyless LCSC metadata plus an EasyEDA symbol/footprint reference, if already known locally), validate it, and write it to the local device cache (confirmWrite required). Does NOT verify pin/pad geometry — see docs/catalog-ingestion.md.

Inspect live schematic component objects, including available methods and state getter values, to validate EasyEDA runtime mappings.

Look up generic engineering reference guidance: IPC-2221 trace-width/current-capacity, clearance bands, protocol routing data (USB/RS-485/I2C/SPI/UART/Ethernet), decoupling recipes and bulk capacitance sizing, and a static DFM checklist. Every result cites a source and caveat: these are estimates, not certified values.

Dev-only: push the freshly built extension dispatcher bundle (dist/dispatcher.js) into the running EasyEDA extension over the bridge, replacing its dispatch logic without re-importing the .eext. action=status reports the active dispatcher build; push sends the bundle at bundlePath (defaults to BRIDGE_HOT_SWAP_WATCH); revert restores the baked dispatcher. Requires BRIDGE_HOT_SWAP_ENABLED=true (refused in production), a dev extension build, and confirmWrite=true on every call (including status).

Run EasyEDA Pro's native PCB DRC and refresh its visible DRC panel. Requires a PCB document to be focused; otherwise returns an indeterminate not_available result with an actionable focus error. Returns coarse severity counts; per-violation detail stays in EasyEDA Pro.

Run native schematic ERC and supplement aggregate counts with inferred_floating_pins. Requires a focused schematic. Explicit focused is supported; page/all_pages fail closed on EasyEDA Pro 3.2.149. Native counts remain authoritative; unavailable focus returns not_available.

Execute arbitrary JavaScript in the EasyEDA Pro extension runtime via the Run API Gateway. The code receives `eda` as the EDA API root object. Requires BRIDGE_RAW_EXEC_ENABLED=true, MCP_RAW_EXEC_EXPERIMENTAL=true, bridge:execute scope when TOOL_SCOPES is set, and confirmWrite=true. Use this when typed API methods are unavailable or to run multi-step sequences atomically.

Export PCB design to Gerber files for PCB fabrication.

Export the schematic netlist in a specified EDA tool format (PADS, Allegro, or Altium).

Export the schematic and/or board layout to PDF.

Export pick-and-place (centroid) file for PCB assembly. Contains component reference, position, rotation, and layer.

Return server capabilities, including available profiles, enabled feature flags, and supported operations.

Return current feature flag values.

Return safe (redacted) server configuration. Secrets are never exposed.

List available tool profiles and their descriptions.

Return server health status in one call: runtime version, active profile, bridge state, EasyEDA version, keyless sourcing state, and starter catalog size. Intended as the single actionable status check after first connecting the bridge extension.

Prepare a non-binding JLCPCB quote workflow snapshot with explicit human-review gates and audit evidence. This tool never places orders or performs paid operations.

Preview/apply string-valued Personal Device properties with explicit thumbnail reinsertion. Requires preview fingerprint, image hash and confirmWrite. Verifies saved metadata, identical image bytes and preserved fields. Limited to EasyEDA 3.2.206; never infers engineering approval.

Run a read-only live smoke report against the connected EasyEDA bridge and return status, API inventory, components, wires, and schematic nets in one response.

Exercise real schematic (and optionally PCB) write paths against the bridge — place, connect, wire, delete — reporting pass/fail per step, then clean up its own scratch primitives. Needs a test device from schematic_search_device and the matching tab focused.

Return latency budgets, runtime metrics, cache/vendor timing snapshot, and storage retention policy for performance diagnostics.

Create a native EasyEDA PCB Region/keepout from a typed polygon and documented rule values. This is not a copper pour/zone. Success requires getAll-backed read-back; unconfirmed optional name/lineWidth values cause rollback.

Draw a non-electrical line on the PCB (e.g. Top/Bottom Silkscreen) for section dividers or board art — reuses the same PCB_PrimitiveLine primitive as add_track but with an empty net name, so it never appears in the netlist or ratsnest.

Place a text primitive on a PCB layer (typically Top/Bottom Silkscreen) — reference labels, section titles, assembly notes. Signature recovered from PCB_PrimitiveString: fontFamily must be a name the runtime's font list actually contains — "NotoSansMonoCJKsc-Regular" (the default) is live-verified to work.

Draw a copper track/trace on the PCB board. A multi-point path is written as one line segment per consecutive point pair (all sharing netName, so they form one electrical track — same coordinate/name merge model as schematic wires).

Place a via to connect different copper layers on the PCB board. outerDiameter/holeSize are passed through to the native API unconverted (same native unit as x/y) — their real-world scale was not independently verified against a known physical dimension, so confirm the resulting via size visually before trusting it.

Preview a strictly typed rectangular native copper-zone create plan without any bridge writes. Apply remains unavailable pending complete capability, approval, read-back and recovery gates. Existing zone write requests continue to fail closed.

Drive EasyEDA Pro's native autorouter (PCB_Document.autoRouting, a @beta API) after a pre-flight constraint check, then run DRC and a constraint report before reporting success. Never reports success without that evidence attached (confirmWrite required).

Run PCB constraint validation against the board design. Checks board outline, layer stackup, net classes, clearance rules, keepout areas, placement zones, mounting holes, fiducials, and manufacturing constraints.

Generate a human-readable report explaining which PCB constraints were applied and which require manual review.

Delete components, tracks, vias, or other PCB primitives by ID. Checks each id against every deletable PCB class instead of assuming component, since PCB_PrimitiveComponent.delete() reports success for ids it does not own without deleting them.

Export the board as a Specctra DSN file (PCB_ManufactureData.getDsnFile) — an open, vendor-neutral format supported by external autorouters such as FreeRouting. Re-import the routed result through EasyEDA Pro's own SES/DSN import, not through this server.

Translate CircuitIR physical constraints (keepouts, top/bottom side, connector-edge, thermal spacing) into a component group placement plan, then optionally apply it. CircuitIR devices carry no physical dimensions, so widths/heights must be supplied per device (confirmWrite required).

Preview or apply a PCB component transform for top/bottom side, native X/Y coordinates in mils, and rotation in degrees. Apply requires confirmation, captures a transaction snapshot, verifies fresh native read-back, and restores on mismatch. EasyEDA Pro has no independent component mirror field.

Direct PCB component creation is unavailable because the verified EasyEDA runtime does not complete PCB_PrimitiveComponent.create(). This tool fails closed. Place the part in the schematic, sync to PCB, confirm the native dialog, then reposition it with easyeda_pcb_modify_component.

Create a high-level, constraint-checked placement plan for a group of components and optionally apply it after explicit confirmation.

Run fabrication, assembly, and testability production review rules for PCB handoff. Reports severity-ranked DFM/DFA/DFT findings with actionable remediation before Gerber export or manufacturing submission.

Rebuild existing PCB_PrimitivePour copper via the beta rebuildCopperRegion() API and verify each result through PCB_PrimitivePoured read-back. Requires confirmWrite. PCB rebuilds are not transaction-covered; after timeout inspect before retry. PlaneZone objects are unsupported.

Create a high-level, constraint-checked route path plan for one net and optionally apply it after explicit confirmation.

Verify the live EasyEDA Pro version, focused PCB, exact net membership, supported copper layer and native zone capabilities. This is a read-only diagnostic and never authorizes zone writes or validates the complete board outline.

Run and classify post-write schematic QA after generated edits. Combines native DRC/ERC results with policy-aware classification so duplicate net names, free networks, and unconnected pins are reported as pass/fail/inconclusive instead of raw warning counts.

Analyze supply sources, regulators, loads, protection, bulk capacitance, current budget, dropout, and regulator thermal risk. Returns machine-readable issues and a human-readable summary.

Generate testpoint checklist, assembly notes, bring-up plan, production QA checklist, and machine-readable QA manifest for board handoff.

Open an in-memory, document-scoped transaction for snapshot-backed schematic writes. Only tools passed transactionId participate; standalone schematic writes are not auto-captured. Only one active transaction is allowed per document. Beginning a transaction does not modify EasyEDA.

Finalize a transaction after its writes and validation gates succeed. Commit removes rollback eligibility and releases the document transaction lock.

Read transaction state, validation results, operation hashes, and rollback status without exposing captured primitive snapshots.

Controlled write: restore applied schematic primitive snapshots in reverse order, verify each restored hash, and report partial rollback explicitly instead of hiding inconsistencies.

Explicitly save the current EasyEDA Pro project. This ensures all netlist changes, net flags, pin connections, and other mutations are persisted to the project file. Save is never implicit — the caller must explicitly request it. Requires confirmWrite.

Run transaction consistency gates before commit: bridge availability, pending/failed operation checks, optional expected operation count, and optional requirement for at least one applied write.

Get a summary of all design and electrical rule check results for the project.

Run internal self-test to verify server integrity, config, and bridge connectivity.

Draw a circle on the schematic sheet — decorative marker or custom symbol element. Cosmetic only, no electrical meaning. fillColor "none" leaves it unfilled.

Draw a closed polygon on the schematic sheet from 3+ vertices — custom decorative shapes, callout arrows, or block diagram elements. Cosmetic only, no electrical meaning.

Draw a rectangle on the schematic sheet — section dividers/grouping boxes for organizing a busy schematic into labeled functional blocks (pair with add_text for the title). Cosmetic only. x/y is the top-left corner; fillColor "none" leaves it unfilled.

Place free-standing text on the schematic sheet (section headers, notes, block labels) — cosmetic/organizational, not a net label. color must be a hex string and fontName a real font (e.g. "Arial") — untyped placeholders create nothing despite returning ok.

Add a wire connecting schematic coordinates/pins — real native connectivity. Same `netName` connects pins globally: separate stubs sharing one name merge into one net (no label needed). NET_COLLISION guards touched points against a foreign net's wire, pin, or flag/port — not mid-segment crossings.

Read the live schematic without modifying it, build a canonical model, and report imported net aliases, duplicate or missing references, unresolved metadata expressions, missing values/footprints, and ambiguous BOM classification. Includes a preview only; it never renames nets or changes components.

Apply up to 200 validated schematic create, modify, pin no-connect, and delete operations in one snapshot-backed transaction. Any failure rolls the whole transaction back. Delete is limited to safely recreatable drawing primitives.

Frame and capture the complete schematic sheet with a sheet-to-image transform. Oversized PNGs are downsampled without cropping; transforms use final image dimensions. Guessed geometry is opt-in.

Scan every component's real pin coordinates and report any (x,y) shared by two or more components — a silent-short risk the native NET_COLLISION guard misses for never-wired pins. Run after manual placement outside easyeda_workflow_* tools (which reconcile this automatically).

Validate a candidate placement (rendered bounds, clearances, conflicts, deterministic alternatives) or -- when x/y are omitted -- search for a safe region of the given size, against real title-block/page-border/existing-primitive constraints. Read-only, no writes.

Get exact pin primitive IDs, numbers, names, coordinates, native no-connect state, and pinType for a schematic component by its primitive ID. pinType is EasyEDA's own symbol-library field and is unreliably authored (often "Undefined" even on real ICs) — treat it as a weak hint, not ground truth.

List schematic components with IDs, references, values, footprints, placement, and project-instance device IDs. Omitted scope preserves legacy all-pages; focused/all_pages are supported, pageUuid is not. Project-instance device IDs are not valid place_component deviceItem values; use schematic_search_device.

Create real EasyEDA connectivity for a pin: draws a short wire stub from its exact coordinate, tagged with netName. Same-netName wires merge globally, so this joins the pin to everything else on that net — visible to ERC, ratsnest, and autorouting.

Bulk variant of connect_pin_to_net: draws a real wire stub from each pin, tagged with netName, so all listed pins (and anything else already on that net) merge into one net. Visible to ERC, ratsnest, and autorouting. A pin that fails (e.g. collision) is reported in failures rather than aborting the batch.

Compute a deterministic connectivity fingerprint (pin/net membership, wire endpoints, labels/ports, no-connects) from the live schematic. Pass the hash as beforeFingerprint/afterFingerprint to easyeda_schematic_layout_qa to prove a cosmetic move left connectivity unchanged.

Create a named net flag/label. With `identification` (Power/Ground/AnalogGround/ProtectGround) it places a power-flag symbol binding to a coincident pin (use for VCC/GND). Without it, a generic net label — cosmetic only; connect pins with add_wire stubs sharing one netName.

Place a hierarchical net port (off-sheet connector) on the schematic. Net ports create named connections that span multiple schematic sheets, appearing as real SCH_Net entries in the netlist.

Delete components, wires, or other drawing objects by primitive UUID. Pass projectId + transactionId for rollback-backed deletion of safely recreatable drawing primitives; unsupported transactional delete kinds fail before mutation. Without transactionId the write is standalone.

Detect title-block overlap, page-boundary overflow, and component-overlap violations from real rendered bounds, and propose cosmetic-only moves that resolve them. Read-only preview only (requiresConfirmWrite=true, no writes) -- confirmWrite apply with connectivity-fingerprint rollback is tracked separately (#273).

Apply the layout-autofix cosmetic moves in a snapshot-backed transaction, re-verifying a connectivity fingerprint after every write batch. Any unintended electrical change or write failure rolls the transaction back and is reported, never thrown. dryRun:true previews only.

Run a normalized post-write QA pass combining runtime DRC/ERC, expected component/pin topology, rendered primitive bounds, title-block and page constraints, wiring/grouping checks, and connectivity fingerprints, with optional full-page visual evidence. Critical geometry or connectivity findings always block commit.

Safely modify a schematic primitive while preserving omitted fields. With transactionId and projectId, capture before/after snapshots and automatically restore the prior state if the write or post-write read fails. Component moves keep connected wires attached.

Get full details for a specific net in the current schematic context including connected pins and components. Explicit focused scope is supported; page/all_pages scopes fail closed on EasyEDA Pro 3.2.149.

List nets from the current schematic context. Explicit focused scope is supported; page/all_pages scopes fail closed on EasyEDA Pro 3.2.149.

Place a searched library device on the active schematic. Use deviceItem from schematic_search_device; project-local identities from schematic_components are invalid. On timeout inspect reconciled/unconfirmed before retrying. projectId + transactionId enables rollback; without transactionId the write is standalone.

Deterministically plan functional-block placement (reserved rectangles, support space, grid-aligned coordinates, occupancy map, A3 fallback, score) from real sheet/primitive geometry -- no writes. Caller supplies roles/blockId/parentId; other primitives read as occupied regions, never overwritten.

Compute a safe schematic drawing region before placing components. Uses live sheet info when available, assumes EasyEDA bottom-left coordinates, reserves the default lower-right title-block keep-out, and returns an anchor/bounds plan that avoids title-block overlap.

Read the live schematic and produce a deterministic, read-only normalization plan with a stable plan ID, model hash, proposed net-name/reference/metadata operations, validation gates, warnings, and blockers. This tool never writes to EasyEDA.

Read real rendered (sheet-space, rotation-aware) component bounding boxes from the live bridge, batched in one call. Origin is not a collision bound -- use combinedBounds for overlap/page/title-block checks. Reference/value text is not independently addressable here and reports not_available.

Search for schematic symbols/devices in the EasyEDA library by keywords. Full results carry the library's complete metadata object per device; pass minimal:true to get back only uuid/libraryUuid/name/pin_count/symbol_type when that is all you need.

Set or clear EasyEDA Pro's native No Connect marker on one exact component pin. This changes the component pin noConnected state; it does not create a net, label, power flag, or short-circuit flag. The bridge rejects missing/ambiguous pins and verifies the native readback after the write.

Update schematic title block text fields (Company, Version, Drawn, Reviewed, Page Size). Only these 5 are exposed — writing Symbol/Border/Device/etc once corrupted a real title block; those are read-only natively and must be fixed via the EasyEDA Pro UI.

Return read-only schematic sheet metadata. Supports focused, pageUuid/page, and all_pages page-list reads without changing EasyEDA focus; aggregate geometry is never invented.

Request a schematic-to-PCB sync (SCH_Document.importChanges). CAUTION (live-verified): opens a confirmation dialog in EasyEDA Pro's UI a HUMAN must approve — success here only means the request was sent, not that components appeared. Ask the user to approve the dialog, then verify with pcb_components.

Validate inferred nets/floating pins and cross-check native ERC. Only native noConnected=true excludes a pin; unavailable/malformed state stays visible. `valid` requires clean inference and zero native errors. Explicit focused is supported; page/all_pages fail closed on EasyEDA Pro 3.2.149.

Read back schematic state after an agent-authored write. Returns component-count delta evidence and optional netlist validation so agents can confirm a placement or connection before continuing.

List wire segments with primitiveId, coordinates, net, color, and style; paginate past 50 with offset. Explicit focused is supported; page/all_pages fail closed on EasyEDA Pro 3.2.149. primitiveId is required by delete_primitive/modify_primitive.

Extract nets/devices/pins from the LIVE schematic and run semantic ERC — no hand-authored netlist needed. Net/pin electrical types are INFERRED from naming conventions, not verified — treat findings as a first-pass signal, not a substitute for semantic_erc_validate.

Run semantic electrical-rule validation over a netlist with pin electrical types to detect output contention, floating inputs, power conflicts, missing power pins, missing decoupling, and voltage-domain mismatches.

Translate a typed circuit description into a SPICE deck and run an offline ngspice operating-point (.op) simulation, optionally checking rail node voltages against a spec. Read-only, local-only. Reports a capability gap rather than failing when ngspice is absent.

Translate a typed circuit description into a SPICE deck and run an offline ngspice transient (.tran) simulation, optionally checking the final rail voltage against a spec. Read-only, local-only. Reports a capability gap rather than failing when ngspice is absent.

Inspect live schematic wire objects, including line coordinates, net names, methods, and state getter values, to validate EasyEDA runtime mappings.

Place a connector, wire each declared pin to its net, and create a net port for each net so the breakout is accessible off-sheet — all as a single atomic transaction (confirmWrite required).

Place one decoupling capacitor per declared IC power pin and wire each to the pin's net and ground, in a single atomic transaction. Cites design-rules decoupling guidance (rule-of-thumb, not datasheet-specific) alongside the plan (confirmWrite required).

Compute and create a section rectangle + title sized from the real pin extents of the given already-placed components (or replace an existing rectangle/title pair). Reports overlap with other rectangles and page-size overflow as warnings; never resizes the page.

Create a deterministic LED blinker workflow: a switch, current-limiting resistor, and indicator LED. Uses safe sheet-region planning, left-to-right layout, generic wire stubs, and optional post-write QA. Caller supplies resolved device items (confirmWrite required); simplest circuit for validating the MCP pipeline.

Create a deterministic NE555 astable LED flasher workflow using safe sheet-region planning, component-level layout offsets, explicit pin-to-net connectivity, and optional post-write QA. Caller supplies already-resolved EasyEDA device items; this tool does not guess catalog parts (confirmWrite required).

Place a group of components, wire their pin-to-net connections (new and/or pre-existing components), and create net ports for block-external nets — all as a single atomic transaction with rollback on partial failure (confirmWrite required).

Place a regulator and its supporting passives and wire them to input/output/ground nets in a single atomic transaction, instead of one primitive call per component. Caller supplies already-resolved device items and pin connections; this tool does not select parts (confirmWrite required).

Plan or apply an RP2040 servo-module scaffold: 56 BOM parts in seven visible rollback-backed sections with deterministic titles and completeness diagnostics. Exact pin-to-net wiring stays intentionally absent until later block netlists supply it (confirmWrite required).