Multisim MCP

Rank 2-16 complete designs using one evidence-backed experiment contract. Each item must contain exactly ``variant_id`` and ``design``. All requirements are hard constraints, only finite measured passes are ranked, and no source design is modified or automatically adopted.

Numerically compare common signals from two registered EDA experiments.

Compare the best native sweep candidate against the original-value baseline.

Compile an approved logical draft into a bounded pin-level preview. Only options in the compiler support matrix are accepted. External model bytes, when present, are re-hashed beneath ``MULTISIM_MCP_MODEL_ROOT``. The result stays in memory and does not write files, create a schematic, start Multisim, or run a simulation.

List portable built-in and local declarative component adapters.

Connect to the local Multisim Automation API.

Create an editable Multisim schematic from a supported SPICE netlist. Supports RLC components, scalar/waveform voltage and current sources, B/E/F/G/H/T primitives, modeled semiconductors and switches, OPAMP5, and user-local verified TIMER8/LM555CN and DFF8/7474N native carriers, generic two-to-sixteen-terminal X subcircuits, digital devices, ground, named nets, wiring, and deterministic layout. Compatible inline subcircuits are recursively expanded into editable primitives; unsupported macro-model constructs remain explicit carrier-only evidence. Generated schematic probes remain experimental…

Decode a .ms14 file to editable XML using ewd.

Diagnose a circuit without modifying it or silently guessing repairs. Structural checks require only ``design``. When ``experiment_dir`` is supplied, its artifact integrity manifest and canonical netlist are verified before requirement, convergence, BJT, or op-amp evidence is used. An optional bounded ``simulation_failure`` object may contain code, type, stage, and message fields from a failed run.

Disconnect from Multisim and release the open circuit.

Run an unrestricted Multisim command file when explicitly enabled. This advanced tool is disabled by default because command files can access the filesystem and may expose engine-specific command execution features.

Encode an XML design back to .ms14 using ewe.

List component reference designators. 0 returns all.

List simulation inputs. 0 returns all.

List simulation outputs. 0 returns all.

Retest one explicit reversible patch against its unchanged baseline. The service runs exactly two verified experiments under the same hard requirements, writes before/after deterministic diagnoses and an inverse patch, and never persists the candidate as the source design. A passing result remains subject to the separate local approval workflow.

Export an artifact beneath MULTISIM_MCP_ARTIFACT_EXPORT_DIR.

Export bilingual HTML/PDF reports and a reproducibility manifest.

Export a bilingual native sweep comparison report and integrity manifest.

Write a Markdown report for the open circuit and analysis results.

Export the circuit schematic as an image.

Return durable progress, failure diagnostics, or the completed result.

Return a compact report, verification, and artifact summary for agents.

Fetch data for an output that is ready; shape depends on analysis type.

Read the current value of an R/L/C component through RLCValue.

Run auditable mixed topology/value multi-objective global optimization. When ``requirement_review`` is supplied, its verified hard constraints and matched soft objectives fill the multi-objective spec before validation. Small declared domains are exhaustive; larger domains use deterministic Halton space filling. Every candidate runs a real verified experiment, failed hard constraints are excluded, and the result contains an epsilon-aware Pareto front. No candidate is persisted automatically.

List the sheet position (x, y) of every component in an .ms14 file. Decodes the design with the packaged ewd codec and reads each component symbol's translation pair (Transformer-M20/M21). No Multisim session is required. With ``output_xml`` the decoded XML is also written there for offline inspection.

List artifact metadata, hashes, MIME types, and safe access capabilities.

List recent durable jobs without returning their potentially large results.

Compute explicit metrics from a registered experiment's raw data.

Create a new empty Multisim design.

Open a Multisim design file and return circuit info.

Evaluate bounded component-value candidates without modifying the source design. The baseline consumes one experiment from ``spec.max_experiments``. When ``requirement_review`` is supplied, its verified hard constraints and a uniquely matched soft objective fill the spec before validation. Values may be explicit or generated from bounded E12/E24/E48/E96 ranges. Electrical, optional in-stock, and maximum variable-cost rules are hard constraints; failed/unverified candidates are never feasible, and the returned best patch still requires the separate local approval workflow before persistence.

Minimize bridge capacitance by native experiments, tolerance cases and saved-file replay. Preview discloses nine discrete candidates and fixed input/load/capacitance cases. Execution may take several minutes. Keeps every failed candidate, checks startup, reopens the selected saved circuit and exports comparison reports. No physical certification.

Return comparable technical方案 without generating or executing a circuit. The result is a bounded planning-only ``DesignPlan``. It contains a deterministic recommendation, alternative implementation paths, trade-offs, and explicit assumptions. Netlists, schematics, files, and simulations are intentionally deferred until a caller selects an option in a later step.

Validate and preview parameter, tolerance, temperature, or Monte Carlo runs.

Use a configured model to propose a requirement, then validate it locally. The model receives one narrow tool and cannot return a schematic, file path, shell command or executable SPICE. The resulting proposal is still only a plan until native execution is requested separately.

Validate a structured multi-board request and return a planning-only contract. This tool never opens Multisim, writes a project, or starts simulation. A feasible candidate may include board-local logical artifacts, but native generation and acceptance remain a separate explicit step.

Translate a bounded sensor analog-front-end request into a native proposal.

Plan a bounded single-NPN common-emitter amplifier request.

Translate a bounded DC divider request into a native proposal.

Translate a bounded natural-language electrical request into a validated plan. The returned netlist is a proposal only. Callers must review it, create the native schematic, and run native measurements before accepting a design. Ambiguous requirements fail closed instead of selecting an unverified topology.

Build a bounded non-inverting OPAMP5 contract and SPICE preview.

Plan a 4–18 Vrms, 50/60 Hz 1N4001GP bridge with a 5–200 mA resistive load.

Build a bounded RLC contract and SPICE preview without native execution. Native RLC acceptance remains disabled until the corresponding Multisim measurement adapter has passed a real-version regression.

Prepare a reviewable electrical specification from a selected plan. This read-only step lists required electrical parameters, planned modules, analyses, and validation gates. It requires a valid selection digest and never creates a CircuitDesign, netlist, schematic, file, or simulation.

Prepare a standard reversible DesignPatch from the best native sweep result.

Prepare a logical netlist draft after explicit specification approval. The result contains block-level nets, connections, unresolved component requirements, and derived constraints. It is not executable SPICE and never creates a CircuitDesign, schematic, file, or simulation.

Rank completed native sweep records against an explicit scalar objective.

Read one bounded page from an allowlisted text experiment artifact.

Read DC, true RMS, AC RMS and range from experiment data.

Register an existing complete experiment directory as MCP Resources. Use this after a server restart when the experiment was generated earlier. Only the fixed high-level experiment artifact set is exposed.

Register a completed sweep directory and return opaque MCP Resources.

Export the bill of materials to a text file.

Export the SPICE netlist to a text file.

Resolve logical roles into reviewable component candidates and rating gates. This remains a read-only planning step. It does not choose a silent part number, create a CircuitDesign, generate SPICE, write a file, or start a simulation. A later stage must provide model provenance and explicit human approval before compiling an executable netlist.

Queue a fresh attempt using a failed, cancelled, or timed-out job spec.

Review an optimisation contract before running a baseline experiment. The tool normalises measurement requirements, separates hard constraints from soft objectives and preferences, and detects obvious contradictory bounds for the same signal. It never creates a circuit, writes files, or starts a simulation; a clean result only means the declared contract is internally coherent.

Run AC analysis at a single frequency.

Run AC sweep and return frequency/real/imag rows.

Build and run an explicit ngspice behavioral reference in one call. This workflow is intentionally opt-in: it only accepts a netlist containing a supported native ``DFF8``/``7474N``-family carrier, converts that carrier to the portable ``@DFF`` reference, and then runs the converted netlist through the explicitly selected ngspice backend. The source design is not modified, and the result must not be interpreted as native Multisim 74LS74 timing or electrical-equivalence evidence.

Create a schematic, run a safe Multisim analysis, and export a report. This synchronous compatibility tool blocks until completion. For queueing, progress, cancellation, persisted state, and worker recovery, prefer ``submit_circuit_experiment``.

Run DC operating point analysis for the given outputs.

Run a transactional parameter, tolerance, temperature, or Monte Carlo sweep.

Build and verify a composed linear analog design in native Multisim 14.3. The host AI translates the user's request into proposal fields: title, application, netlist, probe_nets, experiments (op/ac with commands), checks. Accepts up to 64 R/C/L, DC/AC voltage sources and ideal OPAMP5 devices in any connected topology. Also accepts explicit LM324AJ from a licensed local template pack, with native model identity verification and OP/AC/TRAN sampled checks (no independent ideal-model equivalence). Other vendor models and semiconductors are rejected. Checks contain analysis, net, quantity, min/max…

Model-propose, locally validate, then optionally run the native RC flow.

Run or preview native acceptance for a selected structured multi-board request. The request is re-planned and a structurally ready candidate is selected before any schematic or COM work. Preview mode is side-effect free. Execution opens, saves, reopens, reads back and simulates each board in the installed Multisim version, then compares explicit fixture observations and a full-design reference. ``analysis`` accepts ``dc`` (default), ``tran`` or ``ac``. Native results retain complete sampled axes; TRAN and AC compare every aligned sample (AC compares real and imaginary parts) without interpo…

Run an approved, bounded COM sweep and restore every original R/L/C value.

Generate and verify a sensor front end from Chinese/English requirements.

Build a bounded 2N3904 amplifier and verify native OP/AC/pulse measurements. Requires a licensed local pack with VDC and VPULSE carriers. Saves the editable schematic, PNG, raw measurements, model/pin checks and report. Success verifies declared sampled conditions; visual review is still needed.

Generate and verify a resistive DC divider from a natural-language request.

Preview or execute supported natural RC requirements in a new output directory. Explicit execution generates .ms14 files, runs native OP/AC/TRAN for bounded candidates and exports acceptance evidence. No external AI model or source- netlist simulation fallback is used. Review disclosed assumptions in preview.

Preview or execute the bounded non-inverting OPAMP5 native workflow.

Build a local native bridge, export its schematic/report and verify OP/transient evidence. Requires licensed AC_VOLTAGE and full 1N4001GP carriers. Checks saved values, diode models/pins, input RMS, DC mean, ripple, resistive load current and settling. Preview by default. This bounded simulation does not certify a physical power supply.

Preview or execute bounded RLC candidates with native Multisim acceptance.

Run SPICE through Multisim or ngspice with safe analysis commands. The default path rejects scripting, shell escapes, file commands, and arbitrary command sourcing. Unrestricted engine commands require both the ``unsafe_commands`` argument and an explicit server-side environment flag.

Run a transient simulation and return downsampled time/real data.

Run an ExperimentSpec and persist evidence-backed requirement verdicts. When the three approval inputs are supplied, the exact executable-netlist and simulation-plan handoff is revalidated before any schematic or simulation work begins. The legacy direct-spec path remains available for compatibility; it does not claim this additional approval provenance.

Check local EDA runtime compatibility without starting Multisim.

Save the circuit, optionally to a new path.

List native component families available to the schematic generator.

Lock one planning option without generating or executing a circuit. The input plan digest is checked before selection. The returned envelope binds the source and selected digests so a later generator can require an explicit, untampered handoff.

Lock a structurally ready multi-board candidate without native execution.

Move components inside an .ms14 file to new sheet coordinates. ``positions`` maps refdes -> [x, y] in sheet units (the builder's auto-layout grid step is 270 x 216; use ``list_component_positions`` to read current values). ``mode="relative"`` treats the values as deltas; ``anchor="pin_center"`` matches the builder's component_positions anchor; ``snap`` rounds onto a grid (9 pt = the builder's normalization grid). Batch-safe: any number of components moves in ONE decode/edit/encode cycle. Attached wires are re-routed with the same obstacle-aware router used at build time. Per Multisim's wir…

Inject a raw (time, value) waveform into a simulation input.

Inject a sampled waveform into a simulation input.

Configure an output request before RunSimulation.

Set an R/L/C component value through SetRLCValue.

Enlarge (or shrink) an .ms14 design's page and GUI working area. Sizes are inches at 96 dpi. Both page stores are kept in sync: the CircPrefs sheet dimensions that drive the image/export API and the DesignSheet WorkArea rectangle the GUI displays (a fixed A4 work area used to clip larger schematics on screen). Components are not moved. When ``output_ms14`` is omitted the source file is updated in place after a one-time ``*.sheet-backup.ms14`` copy is saved next to it.

Export the open Multisim circuit into a validated design snapshot. The source ``.ms14`` remains untouched. The exported netlist and snapshot are written only below ``output_dir``; COM enumeration is retained as evidence alongside the parsed ``CircuitDesign``.

Stop the currently running simulation.

Queue durable model-planned correction with round-level recovery. The persisted provider configuration is validated and secret-free: it contains only endpoint/model metadata and environment-variable names. API keys are resolved by the isolated worker and are never written to job state. Completed rounds are evidence-revalidated; an incomplete planning round is replanned in a new attempt directory. No patch is applied automatically.

Queue a durable, cancellable experiment in an isolated worker process. Prefer this tool for long experiments. Poll ``multisim://jobs/{job_id}`` or call ``get_experiment_job``. Completed jobs return the same experiment result and resource handles as ``run_circuit_experiment``. When approval artifacts are supplied, all three are persisted with the job and verified again inside the isolated worker before execution.

Queue a durable optimization with candidate-level crash recovery. Completed candidates are evidence-verified and reused after a worker or MCP restart. An interrupted candidate is rerun in a new attempt directory. The result still returns only a proposed patch and never modifies the design. Set ``resume_existing`` only to adopt a matching interrupted output folder.

Queue a durable sweep in the same isolated, cancellable worker system.

Queue durable mixed topology/value Pareto optimization. Completed candidates are integrity-checked and reused after restart. An interrupted candidate is rerun in a new attempt directory. No recommended patch is persisted into the source design automatically.

Queue an auditable model-to-Multisim engineering run. The worker persists the model plan before native execution and exposes the same durable status/SSE contract as other long-running experiment jobs.

Queue a native RC, RLC, or OPAMP engineering workflow.

Dry-run a custom layout and report geometry findings in seconds. Runs the real builder (obstacle-aware routing included) into a scratch directory -- no Multisim launch, no files kept -- and returns the geometry preflight: final placements, component-overlap pairs, wire-through-body points and the resulting sheet size. Use it to iterate on a ``positions`` map cheaply before the minute-scale ``create_schematic_from_netlist`` build + verification cycle (typically 1-3 minutes on a large board -- no Multisim launch, no files kept).

Evaluate explicit design requirements; unsupported evidence stays unverified.