Silica

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npx agentmarket install connector/simaanc-silica-eda

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Use cases: testing, debugging

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What this server can do and what it asks for, from its tool list, install config and code. Checked Oct 25, 2026.

Tools

10 read · 5 write · 0 delete · 3 not yet classified

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Python package

Tools (18)

Read from the source code; the running server may differ. Descriptions are the server’s own words; hidden characters are shown as [U+…].

• capture_serial

  Capture a board's UART output, optionally sending text first. Use after program_device to check what the design prints, e.g. a firmware banner, or that typed characters are echoed. Only the port you name is opened; silica never scans for serial ports. Args: port: Serial device to open, e.g. "/dev/ttyUSB1" or "/dev/serial/by-id/usb-...-if01-port0" (Linux), "COM4" (Windows). On boards with an FTDI JTAG+UART bridge the UART is usually the second interface (if01). baud: Baud rate; 8N1, no flow control. duration: Seconds to listen (at most 600). send:…

• doctor

  Report silica's version and which EDA tools it can use, with a fix for each gap. Call this first in a new environment, or when a tool call says a tool is missing, to see what is installed before choosing a flow. It finds tools the same way the other tools do (PATH, then an OSS CAD Suite install) and asks each open-source tool for its version. Commercial tools (VCS, Questa, Xcelium, Vivado, ...) are only looked up, never run, so no license is checked out. Takes a few seconds. Args: check_updates: Also ask PyPI (3 s timeout) whether a newer silica-eda exists. Offline or blocked net…

• format_rtl

  Auto-format a SystemVerilog/Verilog file and return a unified diff. Call with dry_run=True first to review the diff, then dry_run=False to write the formatted source back. The file must stay inside the project directory (same confinement as write_rtl). Args: file: Path to the source file to format. dry_run: If True (default), return the diff without writing. If False, overwrite the file with the formatted output. tool: "auto" | "verible". Auto uses config priority order. timeout: Seconds before killing the formatter. Returns: {dry_run, written, diff, lines_c…

• get_constraints

  Read and return the content of a constraint file (.xdc / .sdc / .lpf / .upf). Args: file: Path to the constraint file; must stay inside the project directory. Returns: content: raw file text, path, format (inferred from extension)

• get_project_structure

  List the project's RTL and constraint files. Start here in an unfamiliar project to find the sources to pass to lint, run_simulation and synthesize, and the constraint file for run_place_route. Args: root: Directory to scan, inside the project (defaults to the project root). Returns: root: the directory scanned (absolute) rtl_files: relative paths of .v/.sv/.svh/.vh/.vhd/.vhdl files constraint_files: relative paths of .xdc, .lpf, .sdc, .upf and .pdc files (iCE40 .pcf files are not listed) file_count: number of RTL files error: present only when root…

• launch_waveform

  Open a VCD/FST/FSDB trace file in a waveform viewer (fire-and-forget). Typical flow: 1. result = run_simulation(..., trace=True) 2. launch_waveform(result["trace_vcd"]) Args: trace_file: Absolute path to the .vcd, .fst, or .fsdb trace file. viewer: "auto" | "surfer" | "gtkwave" | "verdi". Auto picks from config priority order. Returns: {"viewer": str, "launched": bool, "trace": str} or {"launched": False, "error": str} on failure.

• lint

  Lint a SystemVerilog/Verilog file and return structured warnings. Args: file: Path to the source file to lint. May instead be a ``.f`` filelist (one path per line); each listed file is linted. ruleset: "default" | "all" | comma-separated rule list (tool-specific). tool: "auto" | "verible" | "verilator" | "svlint" | "spyglass". Auto uses config priority order. timeout: Seconds before killing the linter (applied per file). extra_files: Additional files to lint. Each may itself be a ``.f`` filelist, expanded in place. Warnings across all files ar…

• program_device

  Program a bitstream to an FPGA device with openFPGALoader. Loads volatile SRAM by default, which is safe to repeat. For Xilinx devices success means the FPGA asserted DONE; a rejected bitstream is reported as a failure even though openFPGALoader exits 0. The design starts running as soon as loading finishes, so boot output is usually missed by a serial capture started afterwards (see capture_serial). Args: bitstream: Path to a loadable bitstream from run_place_route: .bit (Xilinx, ECP5) or .bin (iCE40). nextpnr's .asc/.textcfg text configs can't be loaded di…

• read_coverage

  Summarize a Verilator coverage.dat as structured line coverage. Typical flow: 1. result = run_simulation(..., simulator="verilator", coverage=True) 2. read_coverage(result["coverage_dat"]) # find the weak spots Args: coverage_dat: Path to the coverage.dat produced by a coverage run (the run_simulation result's coverage_dat field). max_uncovered: Cap on uncovered line numbers reported per file; "uncovered_truncated" is set when the cap is hit. timeout: Seconds before killing verilator_coverage. Returns: {coverage, total {lines_to…

• read_rtl

  Read an RTL file, optionally restricted to a line range. Args: file: Path to the file; must stay inside the project directory. start_line: First line to return (1-indexed, inclusive). end_line: Last line to return (1-indexed, inclusive). Returns: content: file text with line numbers, path, total_lines

• read_waveform

  Read signal values from a VCD or FST trace — no viewer needed. Typical debug flow: 1. result = run_simulation(..., trace=True) # note failure time T 2. read_waveform(result["trace_vcd"]) # discover signal names 3. read_waveform(result["trace_vcd"], signals=["dut.state", "dut.count"], time_start=T-100, time_end=T+10) Args: trace_file: Path to the trace. VCD is read directly; .fst is converted via the OSS CAD Suite's fst2vcd first. signals: Signal names to read. A name matches on the full hier…

• run_cocotb

  Run a cocotb (Python) testbench against an HDL design. cocotb writes testbenches as Python coroutines instead of an HDL testbench; this builds the design and runs the cocotb tests via cocotb's runner, returning per-test pass/fail. Args: sources: HDL design files. May include ``.f`` filelists (one path per line), expanded in place. test_module: Path to the Python cocotb test file (contains the @cocotb.test() coroutines). toplevel: Top-level HDL module cocotb instantiates. simulator: "icarus" | "verilator" | "ghdl" | "questa" | "xcelium" |…

• run_formal

  Run formal verification or equivalence checking and return structured results. Two usage modes for property verification (sby/jaspergold/vc_formal): 1. Pass sby_file — run an existing .sby or .tcl config file directly. 2. Pass files + top — auto-generate a config and run it. For equivalence checking (tool="eqy"): 1. Pass sby_file pointing to an .eqy config file. 2. Pass gold_files + gate_files + top — auto-generate an .eqy config. Args: sby_file: Path to an existing config file (.sby, .eqy, or .tcl). files: RTL source files for property verification (when sby_file is omitted…

• run_place_route

  Place and route an FPGA netlist and return timing and utilization. Takes a Yosys JSON netlist (from synthesize with target "ice40"/"ecp5"/ "xilinx"/etc.). The output is a bitstream ready for program_device when the packing tool is available: a .bit for xilinx (openXC7's fpga-as), a .bin for ice40 (icepack) and a .bit for ecp5 (ecppack). Without it, the output is nextpnr's FASM or text config (.asc / .textcfg) and a warning says what is missing. Args: netlist: Path to Yosys JSON netlist (produced by the synthesize tool). arch: FPGA architecture — "ice40" | "ecp5" | "nexus" | "machxo2"…

• run_simulation

  Run RTL simulation and return structured diagnostics. The simulator runs in the DUT file's directory, so relative paths in the testbench (e.g. $readmemh("../fw/firmware.hex")) resolve from there, with or without trace/coverage. A failing $fatal/$error comes back in errors with its file, line and message. Args: file: Path to the DUT source file (.sv / .v for Verilog, .vhd for VHDL). May instead be a ``.f`` filelist (one source path per line); its entries become the design sources. testbench: Path to the testbench file. simulator: "auto" | "verilator" | "icarus"…

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Last commit

Oct 22, 2026 (6 days ago)

Last release

Oct 20, 2026 (8 days ago)

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Oct 20, 2026 (8 days ago)

From GitHub (fetched Oct 24, 2026) and the package registry.

Details

Registry name

io.github.simaanc/silica-eda

Version

0.5.0

Auth

No auth

Packages

pypi silica-eda

License

AGPL-3.0

Repository

github.com/simaanc/silica-eda

First seen

Oct 24, 2026

Last checked

Oct 24, 2026

Source

Official MCP Registrygithub-graphql